In response to the escalating complexity of Very Large-Scale Integration (VLSI) chips, He and Luo’s research address the challenges of prolonged and costly design cycles. Leveraging machine learning models such as graph neural networks (GNNs) on netlist representations, they aim to revolutionize chip design methodologies.
Despite the accuracy of current models in predicting critical chip properties like congestion, the lack of explanations for these predictions poses a significant hurdle. He and Luo’s project seeks to enhance the explainability of GNNs, delving into the underlying reasons behind predictions on netlists.
Their research plans to produce interpretable GNNs capable of providing actionable feedback to chip designers, thereby empowering them to optimize VLSI chip designs efficiently.
The Qualcomm Innovation Fellowship, a testament to He and Luo’s scholarly excellence, highlights the significance of their contributions to the field of data science and semiconductor technology.
For further details about the Qualcomm Innovation Fellowship, please visit Qualcomm’s official website.